Interruption control system and method

ABSTRACT

An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

FIELD OF THE INVENTION

The present invention relates to an interruption control system and an interruption control method, and more particularly to an interruption control system and an interruption control method for use with a computer system.

BACKGROUND OF THE INVENTION

Power-saving means is widely used to minimize power consumption in a computer system. Many kinds and levels of power-saving modes are developed to achieve the purpose. One of the examples is so-called as ACPI. ACPI (Advanced Configuration and Power Management Interface) is a specification defining standard interfaces for hardware configuration and power management of the power-saving means. According to the ACPI specification, the central processing unit (CPU) of the computer system operates in various power states, e.g. C1, C2, C3, etc. Different power states result in different levels of power saving effects. For any power-saving mechanism, it is important to reduce power consumption while providing a stable operational environment for circuit at a relatively low temperature.

Generally speaking, the power management for the CPU of the computer system is implemented with the south bridge chip of the chipset. Referring to a conventional computer scheme of FIG. 1, for activating and deactivating power-saving modes, the south bridge chip 2 includes a stop clock control module 20 coupled to the CPU 1 and north bridge chip 3, and an interrupt control device 22 coupled to the stop clock control module 20 and one or more peripheral equipment, e.g. peripheral device 4.

When the operating system (OS) of the computer system is to enter a power-saving state, the CPU 1 issues a sleep command to the south bridge chip 2. In response to the sleep command, the stop clock control module 20 of the south bridge chip 2 asserts a stop clock signal STPCLK# to the CPU 1 via a clock signal pin 21. Once the STPCLK# signal is generated, the CPU 1 issues a stop grant signal STPGNT to the south bridge chip 2 via the north bridge chip 3 through data buses connecting thereto. In response to the STPGNT signal, the CPU 1, as well as the entire computer system, enters the power-saving state so as to reduce power consumption.

Afterwards, the CPU 1 can be awaked when interrupted by any of the peripheral devices. For example, in response to the receipt of an interrupt signal issued by the peripheral device 4 via the interrupt signal pin 40, the interrupt control device 22 of the south bridge chip 2 issues a wake-up signal to trigger the stop clock control module 20 of the south bridge chip 2 to de-assert the STPCLK# signal. Thus, the CPU 1 and the entire computer system are awaked to recover to the normal operation state.

With the increasing number and variety of peripheral devices and promotion of computer performance, new and diverse architectures of computer systems have been developed. For example, the computer system may involve a plurality of input/output advanced programmable interrupt controllers (IO APICs). Particularly, as shown in FIG. 2, peripheral equipment such as peripheral device 6 can be connected to the north bridge chip 3 other than the south bridge chip 2, and respective IO APICs 25 and 50 are arranged in the south bridge chip 2 and north bridge chip 3. The peripheral device 6 is communicable with the north bridge chip 3 via a PCI (peripheral component interconnect)-to-PCI bridge device 5, and the IO APIC 50 is disposed in the PCI-to-PCI bridge device 5. When the interruption signal is issued by the peripheral device 4 connected to the south bridge chip 2 during the power-saving period, the STPGNT signal can be de-asserted via the clock signal pin 21 connected between the south bridge chip 2 and the CPU 1, as mentioned above. The PCI-to-PCI bridge device 5 where the IO APIC 50 is disposed, however, is not coupled to stop clock control module 20 as the IO APIC 25 does. Therefore, the CPU 1 or the computer system cannot be effectively awaked by the peripheral device 6 from the power-saving state to the normal operation state.

SUMMARY OF THE INVENTION

The present invention provides an interruption control system for use with a computer system, which can effectively wake up the computer system from the power-saving state to the normal operation state when any peripheral device issues an interrupt signal.

As is known to those skilled in the art, in the above-mentioned structure, when receiving the interrupt signal issued by the peripheral device connected to the south bridge chip, the first IO APIC of the south bridge chip issues a wake-up signal to trigger the stop clock control module of the south bridge chip to de-assert the STPCLK# signal. Meanwhile, the first IO APIC also issues a message signaled interrupt (MSI), which is an interrupt message of a memory write cycle, to the CPU 1 via a data bus among the south bridge chip, north bridge chip and CPU. Likewise, when receiving an interrupt signal issued by the peripheral device connected to the north bridge chip, the second IO APIC of the PCI-to-PCI bridge device will issue the similar message signaled interrupt (MSI) to the CPU via a data bus between the north bridge chip and CPU.

The present invention relates to an interruption control system for use with a computer system. The computer system comprises a CPU, a north bridge chip, a south bridge chip, a first peripheral device and a second peripheral device. The interrupt control system comprises a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to the first peripheral device and the south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal issued by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to the second peripheral device and the north bridge chip, and in response to a second interrupt signal issued by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

In an embodiment, the interruption control system further comprises a stop clock control module coupled to the first input/output interruption controller and the CPU, optionally asserting a stop clock signal to have said CPU enter a power-saving state and de-asserting said stop clock signal to have the CPU deactivate the power-saving state in response to the wake-up signal from the first input/output interruption controller or the message signaled interrupt from the second input/output interruption controller.

In an embodiment, the interruption status indicating path is an interruption status indicating pin electrically connected between the second input/output interruption controller and the stop clock control module of the south bridge chip for transmitting the message signaled interrupt from the second input/output interruption controller to the stop clock control module.

In an embodiment, the first input/output interruption controller and the stop clock control module are integrated into the south bridge chip.

In an embodiment, the first input/output interruption controller is an input/output advanced programmable interrupt controller.

In an embodiment, the second input/output interruption controller is an input/output advanced programmable interrupt controller disposed in a bus bridge chip between the north bridge chip and the second peripheral device.

In an embodiment, the interruption status indicating path includes a first data bus between the bus bridge chip and the north bridge chip and a second data bus between the north bridge chip and the south bridge chip for transmitting the message signaled interrupt from the second input/output interruption controller to a stop clock control module of the south bridge chip. The stop clock control module optionally asserts a stop clock signal to have said CPU enter a power-saving state and asserts said stop clock signal to have the CPU deactivate the power-saving state in response to the wake-up signal from the first input/output interruption controller or the message signaled interrupt from the second input/output interruption controller.

In an embodiment, the bus bridge chip is a PCI-to-PCI bridge chip.

In an embodiment, the message signaled interrupt is an interrupt message of a memory write cycle.

The present invention relates to another interruption control system for use with a computer system. The computer system comprises a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to the south bridge chip, and a peripheral device coupled to the north bridge chip. The interruption control system comprises an input/output interruption controller and a stop clock control module. The input/output interruption controller is coupled to the second peripheral device and the north bridge chip and issues a message signaled interrupt in response to an interrupt signal issued by the second peripheral device. The stop clock control module is coupled to the CPU via a stop clock signal pin and to the input/output interruption controller via an interrupt status indicating pin, and de-asserts a stop clock signal previously asserted to the CPU via the stop clock signal pin to deactivate a power-saving state of the computer system in response to the message signaled interrupt received via the interrupt status indicating pin.

In an embodiment, the interruption control system further comprises another input/output interruption controller coupled to the stop clock control module for alternatively triggering the stop clock control module to de-assert the stop clock signal in response to an interrupt signal asserted by the first peripheral device. The stop clock control module is integrated into the south bridge chip together with the stop clock control module.

The present invention also relates to an interruption control method of a computer system. The computer system comprises a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to the south bridge chip and a second peripheral device coupled to the north bridge chip via a bus bridge chip. Firstly, a message signaled interrupt is issued in response to an interrupt signal from the second peripheral device. Then, the message signaled interrupt is transmitted to the south bridge chip via a first data bus between the bus bridge chip and the north bridge chip and a second bus between the north bridge chip and the south bridge chip. Afterward, a stop clock signal that is previously asserted by the south bridge chip to activate a power-saving state of the computer system is de-asserted in response to the message signaled interrupt.

In an embodiment, the interruption control method comprises steps of issuing a wake-up signal in response to another interrupt signal from the first peripheral device, and de-asserting the stop clock signal in response to the wake-up signal.

The contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram illustrating a conventional interruption control means of a computer system;

FIG. 2 is a functional block diagram illustrating another conventional interruption control means of a computer system;

FIG. 3 is a functional block diagram illustrating an interruption control system according to a preferred embodiment of the present invention; and

FIG. 4 is a functional block diagram illustrating an interruption control system according to another preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3, an interruption control system according to a preferred embodiment of the present invention is shown. The interruption control system includes first and second input/output advanced programmable interrupt controllers (IO APICs) 25 and 50. A first peripheral device 4 is coupled to the south bridge chip 2 where the first IO APIC 25 is disposed and a stop clock control module 20 is arranged. A second peripheral device 6 is coupled to the north bridge chip 3 via a PCI-to-PCI bridge device 5 where the second IO APIC 50 is disposed. The second IO APIC 50 of the interruption control system communicates with the first IO APIC 25 and the CPU 1 via an interruption status indicating pin 501.

When the computer system is going to enter a power-saving state in response to the request from the operating system (OS), the CPU 1 asserts a sleep command to the south bridge chip 2. In response to the sleep command, the stop clock control module 20 of the south bridge chip 2 asserts a stop clock signal STPCLK# to the CPU 1 via a clock signal pin 21. Once the STPCLK# signal is generated, the CPU 1 issues a stop grant signal STPGNT to the south bridge chip 2 via the north bridge chip 3 through data buses connecting thereto. In response to the STPGNT signal, the CPU 1, as well as the entire computer system, enters the power-saving state, e.g. C2 or C3 mode, so as to reduce power consumption.

Once a first interrupt signal INT1 issued by the peripheral device 4 via an interrupt signal pin 40 is received, the first IO APIC 25 of the south bridge chip 2 issues a wake-up signal to trigger the stop clock control module 20 of the south bridge chip 2 to de-assert the STPCLK# signal. Accordingly, the power-saving state of the computer system is deactivated, and the CPU 1 and the entire computer system are awaked to recover to the normal operation state.

When a second interrupt signal INT2 is issued by the second peripheral device 6 to the PCI-to-PCI bridge device 5 via an interrupt signal pin 60, a message signaled interrupt MSI, which is an interrupt message of a memory write cycle, is generated from the second IO APIC 50. For example, while a low level of the interruption status indicating pin 501 indicates no interruption signal, a high level of the interruption status indicating pin 501 indicates the receipt of the interruption signal from the second peripheral device 6. Via the interruption status indicating pin 501, the message signaled interrupt MSI is transmitted to the stop clock control module 20 of the south bridge chip 2 to de-assert the STPCLK# signal, thereby deactivating the power-saving state of the computer system.

It is understood from the above embodiment, the interruption control system of the present invention can effectively wake up the computer system from the power-saving state to the normal operation state when either the peripheral device coupled to the south bridge chip or the peripheral device not coupled to the south bridge chip issues an interrupt signal.

The embodiment shown in FIG. 3 utilizes an additional pin 501 to convey the interrupt message. Alternatively, the interrupt message can be conveyed via the existent structure according to the embodiment illustrated in FIG. 4. In this embodiment, the message signaled interrupt MSI generated from the second IO APIC 50 in response to the interruption signal issued by the second peripheral device 6 is transmitted to the stop clock control module 20 via a first data bus 30 between the bus bridge chip 5 and the north bridge chip 3 and a second data bus 31 between the north bridge chip 3 and the south bridge chip 2. In response to the wake-up signal from the first IO APIC 25 or the message signaled interrupt MSI from the second IO APIC 50, the stop clock signal STPCLK# is de-asserted from the stop clock control module 20 of the south bridge chip 2 to deactivate the power-saving state of the computer system.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures. 

1. An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device and a second peripheral device, said interrupt control system comprising: a first input/output interruption controller coupled to said first peripheral device and said south bridge chip, and issuing a wake-up signal to said south bridge chip in response to a first interrupt signal asserted by said first peripheral device so as to deactivate a power-saving state of said computer system; a second input/output interruption controller coupled to said second peripheral device and said north bridge chip, and in response to a second interrupt signal asserted by said second peripheral device, generating a message signaled interrupt; and an interruption status indicating path for transmitting said message signaled interrupt from said second input/output interruption controller to said south bridge chip to have said south bridge chip deactivate said power-saving state of said computer system in response to said message signaled interrupt.
 2. The interruption control system according to claim 1 further comprising a stop clock control module coupled to said first input/output interruption controller and said CPU, optionally asserting a stop clock signal to have said CPU enter a power-saving state and de-asserting said stop clock signal to have said CPU deactivate said power-saving state in response to said wake-up signal from said first input/output interruption controller or said message signaled interrupt from said second input/output interruption controller.
 3. The interruption control system according to claim 2 wherein said interruption status indicating path is an interruption status indicating pin electrically connected between said second input/output interruption controller and said stop clock control module of said south bridge chip for transmitting said message signaled interrupt from said second input/output interruption controller to said stop clock control module.
 4. The interruption control system according to claim 2 wherein said first input/output interruption controller and said stop clock control module are integrated into said south bridge chip.
 5. The interrupt control system according to claim 1 wherein said first input/output interruption controller is an input/output advanced programmable interrupt controller.
 6. The interruption control system according to claim 1 wherein said second input/output interruption controller is an input/output advanced programmable interrupt controller disposed in a bus bridge chip between said north bridge chip and said second peripheral device.
 7. The interruption control system according to claim 6 wherein said interruption status indicating path includes a first data bus between said bus bridge chip and said north bridge chip and a second data bus between said north bridge chip and said south bridge chip for transmitting said message signaled interrupt from said second input/output interruption controller to a stop clock control module of said south bridge chip, which optionally asserts a stop clock signal to have said CPU enter a power-saving state and asserts a stop clock signal to have said CPU deactivate said power-saving state in response to said wake-up signal from said first input/output interruption controller or said message signaled interrupt from said second input/output interruption controller.
 8. The interrupt control system according to claim 6 wherein said bus bridge chip is a PCI-to-PCI bridge chip.
 9. The interrupt control system according to claim 1 wherein said message signaled interrupt is an interrupt message of a memory write cycle.
 10. An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip, and a peripheral device coupled to said north bridge chip, said interrupt control system comprising: an input/output interruption controller coupled to said second peripheral device and said north bridge chip and asserting a message signaled interrupt in response to an interrupt signal asserted by said second peripheral device; and a stop clock control module coupled to said CPU via a stop clock signal pin and to said input/output interruption controller via an interrupt status indicating pin, and de-asserting a stop clock signal previously asserted to said CPU via said stop clock signal pin to deactivate a power-saving state of said computer system in response to said message signaled interrupt received via said interrupt status indicating pin.
 11. The interruption control system according to claim 10 further comprising another input/output interruption controller coupled to said stop clock control module for alternatively triggering said stop clock control module to de-assert said stop clock signal in response to an interrupt signal issued by said first peripheral device, said another input/output interruption controller being integrated into said south bridge chip together with said stop clock control module.
 12. The interruption control system according to claim 11 wherein said input/output controllers are both input/output advanced programmable interrupt controllers.
 13. The interruption control system according to claim 10 wherein said input/output interruption controller is disposed in a PCI-to-PCI bridge chip.
 14. The interrupt control system according to claim 10 wherein said message signaled interrupt is an interrupt message of a memory write cycle.
 15. An interruption control method of a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said method comprising steps of: issuing a message signaled interrupt in response to an interrupt signal from said second peripheral device and transmitting said message signaled interrupt to said south bridge chip via a first data bus between said bus bridge chip and said north bridge chip and a second bus between said north bridge chip and said south bridge chip; and de-asserting a stop clock signal that is previously asserted by said south bridge chip to deactivate a power-saving state of said computer system in response to said message signaled interrupt.
 16. The method according to claim 15 further comprising steps of: issuing a wake-up signal in response to another interrupt signal from said first peripheral device; and de-asserting said stop clock signal in response to said wake-up signal.
 17. The method according to claim 16 wherein said wake-up signal is issued by an input/output advanced programmable interrupt controller disposed in said south bridge chip.
 18. The method according to claim 15 wherein said message signaled interrupt is issued by an input/output advanced programmable interrupt controller disposed in said bus bridge chip.
 19. The method according to claim 15 wherein said message signaled interrupt is an interrupt message of a memory write cycle. 